Prashant Nair is an Assistant Professor at the University of British Columbia in Vancouver, Canada

Research Vision

As we process ever increasing amounts of data, memory systems are seen as the prime resource for storing and delivering this data. To this end, the industry has relied on technology scaling to improve memory density. However, at high densities, memory cells tend to become unreliable and the benefits of capacity are offset by a reduction in reliability. Memory systems are also vulnerable to security flaws and designers have performance and power intensive solutions for secure memories. My research looks at enabling efficient reliable and secure memory systems.

Going forward, I would like to continue investigating solutions for security, new memory technologies, and new computing technologies. For instance, reusing the concepts of data encoding and organization for enabling energy-efficient Internet-of-Things architectures. The ideas on reliability can also be extended to new paradigms such as Quantum Computing in which error-correction accounts for a few orders of magnitude bandwidth overhead. One can also look at low-cost techniques for enabling security in scalable memory systems.

Research Interests

Computer Architecture, Memory Systems, Reliability, Internet of Things, Quantum Computing

Memory Reliability Forum at HPCA-2016 in Barcelona, Spain

I organized the Memory Reliability Forum . The speakers were Vilas Sridharan (AMD), Onur Mutlu (ETH), Mattan Erez (UT Austin) and I.

Publications

[2018]

[C15]. 'Attaché: Towards Ideal Memory Compression by Mitigating Metadata Bandwidth Overheads' (pdf, teaser, slides)
Seokin Hong*, Prashant J. Nair*, Bulent Abali, Alper Buyuktosunoglu, Kyu-Hyoun Kim, and Michael Healy
*Both authors contributed equally
Appears in the 51st International Symposium on Microarchitecture (MICRO) (acceptance rate: 74/348 ≈ 21.3%)

[C14]. 'Morphable Counters: Enabling Compact Integrity Trees For Low-Overhead Secure Memories' (pdf, teaser, slides)
Gururaj Saileshwar, Prashant J. Nair, Prakash Ramrakhyani, Wendy Elsasser, Jose A. Joao, Moinuddin K. Qureshi
Appears in the 51st International Symposium on Microarchitecture (MICRO) (acceptance rate: 74/348 ≈ 21.3%)

[C13]. 'SYNERGY: Rethinking Secure-Memory Design for Error-Correcting Memories' (pdf, teaser, slides)
Gururaj Saileshwar, Prashant J. Nair, Prakash Ramrakhyani, Wendy Elsasser, Moinuddin K. Qureshi
Appears in the 24th International Symposium on High Performance Computer Architecture (HPCA) (acceptance rate: 54/260 ≈ 20.8%)


[2017]

[C12]. 'Taming the Instruction Bandwidth of Quantum Computers via Hardware-Managed Error Correction' (pdf, teaser, slides)
Swamit S. Tannu, Zachary A. Myers Prashant J. Nair, Douglas M. Carmean, Moinuddin K. Qureshi
Appears in the 50th International Symposium on Microarchitecture (MICRO) (acceptance rate: 61/327 ≈ 18.7%)

[C11]. 'DICE: Compressing DRAM Cache for Bandwidth and Capacity' (pdf, teaser, slides)
Vinson Young, Prashant J. Nair, Moinuddin K. Qureshi
Appears in the 44th International Symposium on Computer Architecture (ISCA) (acceptance rate: 54/322 ≈ 16.8%)


[2016]

[C10]. 'XED: Exposing On-Die Error Detection Information for Strong Memory Reliability' (pdf, teaser, slides)
Prashant J. Nair, Vilas Sridharan, Moinuddin K. Qureshi
Appears in the 43rd International Symposium on Computer Architecture (ISCA) (acceptance rate: 57/291 ≈ 19.6%)

[C9]. 'Low-Cost Inter-Linked Subarrays (LISA): Enabling Fast Inter-Subarray Data Migration in DRAM' (pdf, slides)
Kevin K. Chang, Prashant J. Nair, Saugata Ghose, Donghyuk Lee, Moinuddin K. Qureshi, Onur Mutlu
Appears in the 22nd International Symposium on High Performance Computer Architecture (HPCA) (acceptance rate: 53/240 ≈ 22%)

[J4/C8]. 'FaultSim: A Fast, Configurable Memory-Reliability Simulator for Conventional and 3D-Stacked Systems' (pdf, slides)
Prashant J. Nair, David A. Roberts, Moinuddin Qureshi
Appears in the ACM Transaction on Architecture and Code Optimization, 2015 (TACO).
Invited paper to the 11th Conference of High Performance Embedded Architectures and Compilers (HiPEAC)
FaultSim is open sourced and available at this git repository.

[J3]. 'Citadel: Efficiently Protecting Stacked Memory from TSV and Large Granularity Failures' (pdf, teaser, poster, slides)
Prashant J. Nair, David A. Roberts, Moinuddin Qureshi
To appear in the ACM Transactions on Architecture and Code Optimization, 2015 (TACO)
Journal extension of "Citadel: Efficiently Protecting Stacked Memories Against Large Granularity Failures" (MICRO-47)
Additional content includes quick correction of single-bit errors and evaluations on HMC-Like, Tezzaron-Like Stacked-Memories


[2015]

[C7]. 'Reducing Refresh Power in Mobile Devices with Morphable ECC' (pdf, slides)
Chia-Chen Chou, Prashant J. Nair, Moinuddin Qureshi
Appears in the 45th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN) (acceptance rate: 50/229 ≈ 21.8%)

[C6]. 'AVATAR: A Variable-Retention-Time (VRT) Aware Refresh for DRAM Systems' (pdf, slides)
Moinuddin K. Qureshi, Dae-Hyun Kim, Samira Khan, Prashant J. Nair, Onur Mutlu
Appears in the 45th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN) (acceptance rate: 50/229 ≈ 21.8%)

[C5]. 'DEUCE: Write Efficient Encryption for Secure Non-Volatile Memories' (pdf, slides) [ Honorable Mention in MICRO Top Picks 2016 ]
Vinson Young, Prashant J. Nair, Moinuddin K. Qureshi
Appears in the 20th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) (acceptance rate: 48/287 ≈ 16.7%)

[C4]. 'Reducing Read Latency of Phase Change Memory via Early Read and Turbo Read' (pdf, slides)
Prashant J. Nair, Chia-Chen Chou, Bipin Rajendran, Moinuddin K. Qureshi
Appears in the 21st International Symposium on High Performance Computer Architecture (HPCA) (acceptance rate: 51/226 ≈ 22.6%)

[J2]. 'Architectural Support for Mitigating Row Hammering in DRAM Memories' (pdf)
Dae-Hyun Kim, Prashant J. Nair, Moinuddin K. Qureshi
Appears in Computer Architecture Letters, 2015 (CAL)


[2014]

[C3]. 'Citadel: Efficiently Protecting Stacked Memories Against Large Granularity Failures' (pdf, slides)
Prashant J. Nair, David A. Roberts, Moinuddin K. Qureshi
Appears in the 47th International Symposium on Microarchitecture (MICRO) (acceptance rate: 53/273 ≈ 19.4%)

[J1]. 'Refresh Pausing in DRAM Memory Systems' (pdf, slides)
Prashant J. Nair, Chia-Chen Chou, Moinuddin K. Qureshi
Appears in the ACM Transactions on Architecture and Code Optimization, 2014 (TACO)
Journal extension of "A Case for Refresh Pausing in DRAM Memory Systems" (HPCA-19)
Additional studies in this journal paper include mathematical insights and discussions on internal DRAM parallelism


[2013]

[C2]. 'ArchShield: Architectural Framework for Assisting DRAM Scaling by Tolerating High Error-Rates' (pdf, slides)
Prashant J. Nair, Dae-Hyun Kim, Moinuddin K. Qureshi
Appears in the 40th International Symposium on Computer Architecture (ISCA) (acceptance rate: 56/288 ≈ 19.4%)

[C1]. 'A Case for Refresh Pausing in DRAM Memory Systems' (pdf, slides)
Prashant J. Nair, Chia-Chen Chou, Moinuddin K. Qureshi
Appears in the 19th International Conference on High Performance Computer Architecture (HPCA) (acceptance rate: 51/249 ≈ 20.5%)


Peer Reviewed Workshop Publications


[W2]. 'FAULTSIM: A fast, configurable memory-resilience simulator' (pdf, slides)
David A. Roberts, Prashant J. Nair, Moinuddin K. Qureshi
Appears in the Memory Forum held in conjunction with International Symposium on Computer Architecture (ISCA-41)

[W1]. 'Citadel: Efficiently Protecting Stacked Memories Against Large Granularity Failures'(pdf, slides)
Prashant J. Nair, David A. Roberts, Moinuddin K. Qureshi
Appears in the Memory Forum held in conjunction with International Symposium on Computer Architecture (ISCA-41)

Theses


[T2]. 'Designing Low Power SRAM System Using Energy Compression' (pdf)
Graduate (Master's Thesis): School of Electrical and Computer Engineering, Georgia Institute of Technology
Advisor and Committee Chair: Prof. Saibal Mukhopadhyay
Committee Member 1: Prof. Sudhakar Yalamanchili
Committee Member 2: Prof. Moinuddin Qureshi


[T1]. 'Performance Evaluation of Embedded Linux on an ARM Processor' (pdf)
Undergraduate (Final Year Project): Department of Electronics Engineering, University of Mumbai
(members ordered alphabetically) Amit Karande, Ankit Bansal, Prashant J. Nair, Shantanu Kulkarni
Advisor: Prof. Y. S. Rao

Secured Highest Marks in the Department (96/100) in this Final Year Project


Service

  • Primary Reviewer : IEEE CAL, ACM-TACO, ACM-TC, SBAC-PAD
  • External Review Committee Member : ISCA 2016
  • Invited Reviewer : ASPLOS 2016
  • Submission Chair : MICRO 2015, MICRO TOP-PICKS 2017

Contact

Email Address: pnair6 [AT] gatech [DOT] edu"

Computer ARchitecture and Emerging Technologies (CARET) Lab,
Klaus Advanced Computing Building, Room 2304,
266 Ferst Drive,
Georgia Institute of Technology,
Atlanta, GA 30332
United States