Prashant J. Nair
Memory Systems Architect
Associate Professor, The University of British Columbia
KAIS 4014, 2332 Main MallVancouver, BC V6T 1Z4, Canada
Biography
Dr. Nair is an Associate Professor at the University of British Columbia (UBC), where he directs the Systems and Architectures (STAR) Lab, and a memory architect at d-Matrix. He is an Associate Editor of IEEE Computer Architecture Letters, General Co-Chair of ISCA 2027, and an Affiliate Fellow at the Quantum Algorithms Institute.
His research sits at the intersection of computer architecture, advanced memory systems, and ML systems, with a focus on improving efficiency for modern AI and high-performance computing. He has contributed to 40+ top-tier publications in venues including ISCA, MICRO, HPCA, ASPLOS, DSN, SC, NeurIPS, ICML, MLSys, and VLDB.
Major Awards
- IEEE TCCA Young Computer Architect Award The highest early-career award 2024
- ISCA Distinguished Artifact Award Paper 2026
- DSN Test-of-Time Award Paper 2025
- HPCA Distinguished Artifact Award Paper 2025
- MICRO Best Paper Nomination Paper 2024
- HPCA Best Paper Award Paper 2023
Recognition
- Hall of Fame member of ISCA, MICRO, and HPCA Inducted into all three as an Assistant Professor 2024–25
- Three IEEE Micro Top Picks honorable mentions 2016, 2019, 2025
Industry Impact
- Raptor 3D-DRAM Architecture Paper Leads the 3D-DRAM architecture of Raptor, the first commercial 3D-DRAM accelerator for generative inference 2026
- JEDEC HBM3 Standard (JESD238) Paper His proposal combining on-die and host error-correcting codes (XED, ISCA 2016) is part of HBM3, the memory used in today's AI accelerators 2022
Latest Updates
- Service: General Co-Chair of ISCA 2027
- ISCA 2026 Distinguished Artifact Award
- ISCA 2026: Three papers, including the first silicon results for Raptor
- NSERC Discovery Grant: Memory-Centric Architectures for Large-Scale ML Inference
- NeurIPS 2025 acceptance: Foresight (adaptive layer reuse for text-to-video generation)
- MICRO 2025 acceptance: RayN (ray tracing acceleration with near-memory computing)
- DSN 2025 Test-of-Time Award and ISCA Hall of Fame
- CBP2025 @ ISCA 2025: Bullseye (a hybrid branch predictor)
- DRAMSec 2025 @ ISCA 2025: Two papers on RowHammer mitigation analysis and defenses
- ICML 2025 acceptance: Dialogue Without Limits (constant-sized KV caches for long responses)
- New arXiv preprint: Context Switching for Secure Multi-programming of Near-Term Quantum Computers
- ISCA 2025: Four accepted papers across RowHammer, quantum simulation, prefetching, and sparse compute
- HPCA 2025: Two RowHammer-defense papers (including a Distinguished Artifact Award)
- Service: External Review Committee member for MICRO 2025
- Service: Program Committee member for HPCA 2025 and ISCA 2025
- Service: Associate Editor, IEEE Computer Architecture Letters
- DATE 2025 acceptance: Slipstream (semantic training acceleration for recommendation models)