Curriculum Vitae

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Overview

  • Associate Professor (with tenure), University of British Columbia (UBC).
  • Leadership: General Co-Chair, ISCA 2027; Associate Editor, IEEE Computer Architecture Letters.
  • Awards: ISCA 2026 Distinguished Artifact Award; DSN 2025 Test of Time Award; IEEE TCCA Young Architect Award (ISCA 2024).
  • Halls of Fame: ISCA, MICRO, and HPCA (8+ papers each).
  • Publications list: see the Publications tab.

Contact

Name
Prashant J. Nair
Position
Associate Professor, The University of British Columbia
Website
https://prashantnair.bitbucket.io
Email
Show email
Address
4014, 2332 Main Mall, University of British Columbia, Vancouver, BC Canada V6T 1Z4

Research and Consulting Interests

Machine Learning Systems (LLMs, Recommenders, Diffusion Models)

  • Algorithm–memory co-design to cut data movement and latency in training/inference (e.g., compact/constant-size KV caches, embedding locality/skipping, layer reuse for diffusion/text-to-video acceleration).

Memory Architectures for AI Accelerators

  • 3D-stacked DRAM accelerators for generative inference, including placement, interfaces with accelerator logic, energy efficiency, and resilience.

Memory Security

  • Practical, low-overhead RowHammer defenses and timing-channel hardening for commodity DRAM and accelerators.

Memory Reliability

  • Robustness for AI/HPC workloads via sparsity-aware protection and mixed-precision resilience; leveraging modern on-die ECC for enhanced resiliency.

Sustainability in Computing

  • Reducing embodied and operational carbon in memory, storage, and machine learning training and inference pipelines.

Quantum Computing Systems

  • Scalable, noise-aware simulation and efficient scheduling/multiprogramming for VQA/NISQ-era systems.
  • Compilation and architecture co-design for fault-tolerant quantum computing.

Appointments

  1. 2025–Present

    Associate Professor (with tenure)

    University of British Columbia (UBC)

  2. 2019–2025

    Assistant Professor

    University of British Columbia (UBC)

  3. 2022–Present

    Affiliate Fellow

    Quantum Algorithms Institute (QMI)

  4. 2017–2018

    Post-Doctoral Researcher

    IBM T.J. Watson Research Center

  5. 2012–2017

    Graduate Research Assistant

    Georgia Institute of Technology

Industry Experience

  1. 2026–Present

    Memory Architect

    d-Matrix

  2. 2016

    Research Intern

    IBM T. J. Watson Research Center

  3. 2015

    Research Intern

    Intel Labs

  4. 2014

    Memory Device Architect (Intern)

    Samsung Architecture Lab

  5. 2013

    Research Intern

    Advanced Micro Devices (AMD) Research

  6. 2012

    Co-Op Intern

    Advanced Micro Devices (AMD) Inc.

  7. 2009–2010

    Graduate Engineering Trainee

    Reliance Infrastructure Ltd.

Education

  1. 2017

    Ph.D., Electrical and Computer Engineering

    Georgia Institute of Technology

    Advisor: Moinuddin Qureshi

    Academic lineage
  2. 2013

    M.Sc., Electrical and Computer Engineering

    Georgia Institute of Technology

    Advisor: Saibal Mukhopadhyay

  3. 2009

    B.Engg., Electronics Engineering

    University of Mumbai

Honors, Awards, and Impact

Field-wide Recognition

  • DSN 2025 Test of Time Award → Recognizes an outstanding paper published 10 years ago at DSN, in the DSN proceedings (research track, practical experience report or tool papers), that has had a sustained and important impact on the theory and/or practice of dependable systems and networks computing research.
  • TCCA Young Architect Award, the highest early career award in computer architecture, presented at ISCA 2024.

Hall of Fame Inductions

  • Inducted into three premier Halls of Fame in Computer Architecture during my time as a tenure-track Assistant Professor.
  • ISCA Hall of Fame (2025) → Awarded to a Researcher with 8+ papers in ISCA Conference.
  • HPCA Hall of Fame (2025) → Awarded to a Researcher with 8+ papers in HPCA Conference.
  • MICRO Hall of Fame (2024) → Awarded to a Researcher with 8+ papers in MICRO Conference.

Paper Awards and Distinctions

  • ISCA 2026 Distinguished Artifact Award → One of Two Distinguished Artifacts (Transpiler-Architecture Co-Design for Fault-Tolerant Quantum Computing).
  • MICRO Top-Picks 2025 (honorable mention).
  • HPCA 2025 Distinguished Artifact Award → One of Two Distinguished Artifacts.
  • MICRO 2024 Best Paper Nominee → One of Five Best Paper Nominees in 497 Submissions.
  • HPCA 2023 Best Paper Award → One of Two Best Papers in 360 Submissions.
  • Second Place, ML-Based Data Prefetching Competition (MLArchSys Workshop at ISCA 2021).
  • MICRO Top-Picks 2019 (honorable mention).
  • MICRO Top-Picks 2016 (honorable mention).

Industry Impact

  • JEDEC HBM3 standard (JESD238) incorporates my proposal combining on-die and host ECC, from the XED paper (ISCA 2016).
  • Raptor, the first commercial 3D-DRAM accelerator for generative inference: leads its 3D-DRAM architecture as a memory architect at d-Matrix (ISCA 2026).

Academic and Teaching Honors

  • ECE Graduate Research Assistant Excellence Award → Award for outstanding research accomplishments during Ph.D. at Georgia Institute of Technology.
  • Finalist at the Qualcomm Innovation Fellowship – 2014.
  • Thank a Teacher Award → For being an exemplary TA during Fall 2012.

Grants and Funding

  1. 2026–2031

    NSERC – Discovery Grant (Individual)

    NSERC

    Beyond Compute: Memory-Centric Architectures to Enable Efficient Large-Scale Machine Learning Inference

  2. 2019–2026

    NSERC – Discovery Grant (Individual)

    NSERC

    Architectural Techniques to Sustain Moore’s Law to Enable Reliable, Secure, and Efficient Memory Systems

  3. 2019

    NSERC – Discovery Supplement (Individual)

    NSERC

    Architectural Techniques to Sustain Moore’s Law to Enable Reliable, Secure, and Efficient Memory Systems

  4. 2020–2021

    DARPA (Defense Advanced Research Projects Agency)

    DARPA

    An Optimized TensorFlow to RTML Compilation Flow

  5. 2022–2027

    Meta Inc. (Gift)

    Meta Inc.

    Software-Hardware Strategies for Enhancing ML Application Resilience

  6. 2023–2025

    National Research Council (NRC) – Applied Quantum Computing Challenge

    National Research Council (NRC)

    Efficient and Scalable Quantum Simulation Frameworks using Smart Data Representation and Computation Reuse

  7. 2022–2027

    Intel Transformative Server Architecture Grant

    Intel

    Transformative Server Architectures for Next-Generation AI Systems

  8. 2023–2026

    NSERC Alliance Grant

    NSERC

    Transformative Server Architectures for Next-Generation AI Systems

  9. 2024–2026

    National Research Council (NRC)

    National Research Council (NRC)

    Paving the Path to Practical Quantum Simulations through Resource Optimizations

Teaching Philosophy

  • I integrate both practical and theoretical elements into my teaching. My goal is to equip students with the ability to apply concepts and solve real-world problems. My coursework emphasizes hands-on experience by incorporating industry-relevant tools. This approach enables students to use modern frameworks to learn key concepts like caching, branch prediction, and performance optimization. I also encourage students to reason about core computer architecture concepts using mathematical frameworks.
  • To foster an inclusive and engaging learning environment, I employ a variety of assessments, including quizzes, labs, and assignments, which cater to diverse learning styles. This approach ensures that students develop the technical and critical thinking skills necessary for success in academia and industry.

Teaching (UBC)

CPEN 511 – Advanced Computer Architecture (Graduate Course)

  • Winter 2024 T2: 21 Lectures and 5 Project Presentations, Class size: 10
  • Winter 2023 T2: 21 Lectures and 5 Project Presentations, Class size: 16
  • Winter 2019 T2: 21 Lectures and 5 Project Presentations, Class size: 16
  • Winter 2018 T2: 18 Lectures and 3 Project Presentations, Class size: 5

CPEN 411 – Computer Architecture

  • Winter 2024 T1: 24 Lectures and 12 Tutorial Sessions, Class size: 80
  • Winter 2023 T1: 24 Lectures and 12 Tutorial Sessions, Class size: 89
  • Winter 2022 T1: 24 Lectures and 12 Tutorial Sessions, Class size: 65
  • Winter 2021 T1: 24 Lectures and 12 Tutorial Sessions, Class size: 68
  • Winter 2020 T1: 24 Lectures and 12 Tutorial Sessions, Class size: 38
  • Winter 2019 T1: 24 Lectures and 12 Tutorial Sessions, Class size: 38

CPEN 311 – Digital Systems Design

  • Winter 2023 T1: 24 Lectures and 24 Lab Sessions, Class size: 113
  • Winter 2021 T2: 24 Lectures and 24 Lab Sessions, Class size: 36

CPEN 211 – Introduction to Microcomputers

  • Winter 2022 T1: 12 Lectures, 7 Lab Sessions, and 3 Lab Proficiency Tests, Class size: 317

Legend

  • CPEN 211: Introduction to Microcomputers
  • CPEN 311: Digital Systems Design
  • CPEN 411: Computer Architecture
  • CPEN 511: Advanced Computer Architecture (Graduate Course)

Term conventions

  • Winter Term 1 (T1) starts at the beginning of September and ends in the second or third week of December, including the final exam.
  • Winter Term 2 (T2) begins in early January and concludes in the second or third week of April, also including the final exam.
  • The Winter Term T2 of the next calendar year is represented by the previous year. For example, Winter 2023 T2 occurs from January to April 2024.

Students

Current Students

  • Meng Wang – Ph.D. Candidate: Systems Infrastructure for Scalable Quantum Computing
  • Muhammad Adnan – Ph.D. Candidate, CGS-D Fellowship Holder: Memory-Efficient Training and Inference for Large AI Models
  • Jeonghyun Woo – Ph.D. Candidate: Secure and Low-Cost Memory Systems and Architectures
  • Yassaman Ebrahimzadeh Maboud – Ph.D. Candidate: Semantic-Based Training Acceleration for Recommenders
  • Mushahid Khan – Ph.D. Candidate, Four Year Fellowship Holder: Quantum Machine Learning Optimization (primary advisor Prof. Olivia Di Matteo)
  • Junsu Kim – Ph.D. Student, J.K. Zee Fellowship Holder (2026): Accelerating Generative Inference Systems
  • James Chuang – Ph.D. Student, Four Year Fellowship Holder: Secure Microarchitecture and Architectural Techniques for AI and Next-Generation Workloads
  • Madhur Kumar – Ph.D. Student: Efficient Compilation and Architectures for the Quantum Computing Stack

Graduated Students

  • Amin Ghasemazar – Ph.D. 2021 (primary advisor Prof. Mieszko Lis): Efficient In-Hardware Compression of On-Chip Data → CEO and Co-Founder, FabriSight
  • Ali Asgari – M.A.Sc. 2023 (primary advisor Prof. Karthik Pattabiraman): Structural Coding for CNNs → Software Engineer, EA Sports Canada
  • Muchen He – M.A.Sc. 2023 (primary advisor Prof. Mieszko Lis): Mitigating Transient Cache Side-Channel Attacks → Engineer, Intel
  • Bolin Wang – M.A.Sc. 2022: Bo-Tree, a Dynamic Merkle Tree for Scalable Memories → Engineer, Stealth Startup
  • Yassaman Ebrahimzadeh Maboud – M.A.Sc. 2021, continued to Ph.D.
  • Muhammad Adnan – M.A.Sc. 2021, continued to Ph.D.
  • Kevin Zhao – B.A.Sc. 2024 (co-supervised with Mieszko Lis) → Engineer, Microsoft
  • Irene Wang – B.A.Sc. 2023: FLuID → Ph.D. student, Georgia Tech
  • Peter Deutsch – B.A.Sc. 2022 (co-supervised with Mieszko Lis) → Ph.D. student, MIT
  • Jacob Yang – B.A.Sc.
  • John Do – B.A.Sc. (co-supervised with Mieszko Lis)

Tools and Resources

  • HPCA 2023 and IISWC 2024: Training Big Sparse Recommendation Models on Commodity Servers — Project page
  • FaultSim: Open-Sourced Fast and Accurate Memory-Reliability Simulator (with AMD Inc.) — GitHub

Invited Talks

  1. October 2026

    Scaling the Memory Wall: Towards 3D-DRAM-Based Accelerators for Efficient Generative Inference

    Keynote at the IBM IEEE CAS/EDS AI Compute Symposium, IBM T. J. Watson Research Center; also a panelist on Optimizing AI Workloads across the Stack

  2. July 2026

    The Memory Substrate of Tomorrow: Resilient DRAM for Secure and Intelligent Computing

    Keynote at ACM SACMAT 2026, Waterloo

  3. April 2026

    Scaling the Memory Wall: Towards 3D-DRAM-Based Accelerators for Efficient Generative Inference

    SAFARI Live Seminar, ETH Zürich (recorded)

  4. 2026

    Towards 3D-DRAM-based Accelerators for Efficient Generative Inference

    Microsoft Research

  5. 2026

    Towards 3D-DRAM-based Accelerators for Efficient Generative Inference

    EPFL

  6. 2026

    Defenses That Backfire: Exposing and Closing Gaps in Memory Security

    EPFL

  7. 2025

    Scaling the Memory Wall for Next-Generation Machine Learning

    MBZUAI

  8. December 2024

    From Bottlenecks to Breakthroughs: Enhancing Memory Systems for Next-Gen Machine Learning

    IIT Bombay

  9. November 2024

    Ender’s Game: Architectural Techniques to Develop Scalable and Secure Memory Systems

    Columbia University

  10. November 2024

    Ender’s Game: Architectural Techniques to Develop Scalable and Secure Memory Systems

    Cornell Tech University

  11. April 2024

    Ender’s Game: Rethinking Strategies for Crafting Secure Memory Systems

    Georgia Institute of Technology

  12. November 2023

    From Bits to Beyond: Crafting Secure and Scalable Memory Architectures for Next-Generation Systems

    University of Pennsylvania

  13. November 2023

    From Bits to Beyond: Crafting Secure and Scalable Memory Architectures for Next-Generation Systems

    UT Austin

  14. November 2023

    From Bits to Beyond: Crafting Secure and Scalable Memory Architectures for Next-Generation Systems

    NYU

  15. October 2023

    From Bits to Beyond: Crafting Secure and Scalable Memory Architectures for Next-Generation Systems

    EPFL

  16. October 2023

    From Bits to Beyond: Crafting Secure and Scalable Memory Architectures for Next-Generation Systems

    d-matrix

  17. May 2023

    Scaling the Memory Wall: Towards Next Generation Architecture and Systems

    AMD

  18. June 2022

    Research in Industry versus Academia: Learning from Cave People, Wheels, and Cars

    Keynote at the Undergraduate Architecture Research Workshop (co-held with ISCA 2022)

  19. October 2018

    Attaché: Towards Ideal Memory Compression by Mitigating Metadata Bandwidth Overheads

    MICRO-51

  20. Aug. 2016

    DVoLT: Dynamic Voltage and Timing for Memory DIMMs

    IBM

  21. 2016

    XED: Exposing On-Die Error Detection Information for Strong Memory Reliability

    during ISCA’16

  22. Aug. 2016

    XED: Exposing On-Die Error Detection Information for Strong Memory Reliability

    IBM

  23. 2016

    On Fault Simulators

    Memory Reliability Forum (Organizer & Speaker) in HPCA’16

  24. 2016

    DMAT: Decoupling DRAM Mats for low-latency

    ArchiTech co-located with ASPLOS’16

  25. 2015

    Reducing Read Latency of Phase Change Memory via Early Read & Turbo Read

    during HPCA’15

  26. 2014

    Citadel: Efficiently Protecting Stacked Memory from Large Granularity Failures

    during MICRO’14

  27. 2014

    Citadel: Efficiently Protecting Stacked Memory from Large Granularity Failures

    during Memory Forum in ISCA’14

  28. 2014

    FAULTSIM: A Fast, Configurable Memory-Resilience Simulator

    during Memory Forum in ISCA’14

  29. Jun. 2013

    ArchShield: Architectural Framework for Assisting DRAM Scaling by Tolerating High Error-Rates

    AMD

  30. 2013

    A Case for Refresh Pausing in DRAM Memory Systems

    during HPCA’13

Media

  1. July 2026

    Why PC Memory is Stuck in 1995 (Unified Memory Explained)

    Interviewed for Techquickie, Linus Media Group

Academic Service

Conference and Editorial Leadership

  • General Co-Chair: International Symposium on Computer Architecture (ISCA) 2027
  • Associate Editor: IEEE Computer Architecture Letters (2025–present)

Program Committee Member

  • International Symposium on High-Performance Computer Architecture (HPCA) 2026
  • International Symposium on High-Performance Computer Architecture (HPCA) 2025
  • International Symposium on Computer Architecture (ISCA) 2025
  • International Symposium on Microarchitecture (MICRO) 2024
  • International Symposium on Computer Architecture (ISCA) 2024
  • International Symposium on Microarchitecture (MICRO) 2023
  • International Symposium on Computer Architecture (ISCA) 2023
  • International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) 2023
  • International Symposium on Microarchitecture (MICRO) 2022
  • International Conference for High Performance Computing, Networking, Storage, and Analysis (SC) 2022
  • IEEE Micro Special Issue on Top Picks from the 2021 Computer Architecture Conferences
  • International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) 2022
  • International Parallel and Distributed Processing Symposium (IPDPS) 2022
  • International Symposium on High-Performance Computer Architecture (HPCA) 2022
  • International Conference on Computer Design (ICCD) 2021
  • International Symposium on Microarchitecture (MICRO) 2021
  • International Symposium on Computer Architecture (ISCA) 2021
  • Annual Non-Volatile Memories Workshop 2021
  • IEEE Micro Special Issue on Top Picks from the 2020 Computer Architecture Conferences
  • International Symposium on Microarchitecture (MICRO) 2019
  • IEEE Transactions on Parallel and Distributed Processing Systems
  • IEEE Computer Architecture Letters
  • ACM Transactions on Architecture and Code Optimization
  • ACM Transactions on Computers

External Review Committee Member

  • International Symposium on Microarchitecture (MICRO) 2025
  • International Symposium on High-Performance Computer Architecture (HPCA) 2024
  • International Symposium on High-Performance Computer Architecture (HPCA) 2023
  • International Symposium on Computer Architecture (ISCA) 2022
  • International Symposium on Computer Architecture (ISCA) 2020
  • International Symposium on High-Performance Computer Architecture (HPCA) 2018
  • International Symposium on Computer Architecture (ISCA) 2016

Invited Reviewer

  • International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) 2016

Chair Roles

  • Submission Chair: International Symposium on Microarchitecture (MICRO) 2015
  • Submission Chair: IEEE Micro Special Issue on Top Picks from the 2016 Computer Architecture Conferences
  • Local-Area Co-Chair: International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) 2023
  • Finance Chair: 2024 IEEE International Symposium on Workload Characterization (IISWC)
  • Publication Chair: 32nd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems

Organizer

  • Tutorial on Training Big Sparse Recommendation Models on Commodity Servers (Co-held with HPCA 2023 and IISWC 2024)
  • Tutorial on Training Big Sparse Recommendation Models on Commodity Servers (Co-held with HPCA 2023)
  • The Memory Reliability Forum Workshop (Co-held with HPCA 2016)

University Service

Internal committee member for the following students

  • Ian Hill – Ph.D. 2020–present
  • Mohammadreza Saed – Ph.D. 2020–present
  • Dingqing Yang – Ph.D. 2020–present
  • Lufei Liu – Ph.D. 2020–present
  • Mohammadhossien Olyaiy – Ph.D. 2020–present
  • Avilash Mukherjee – Ph.D. 2019–present
  • Yuan Hsi Chou – Ph.D. 2019–2025
  • Nikhil Pratap Ghanathe – Ph.D. 2019–2025
  • Deval Shah – Ph.D. 2020–2024
  • Niloofar Zarif – M.A.Sc. 2020–2023
  • Chris Ng – M.A.Sc. 2020–2022
  • Muchen He – M.A.Sc. 2020–2022
  • Zitao Chen – M.A.Sc. 2019–2020
  • Parvez Chanawala – M.A.Sc. 2020–2022
  • Niranjhana Narayanan – M.A.Sc. 2019–2021

External committee member for the following students

  • Abdelrahman Hussein; Simon Fraser University (SFU) - M.A.Sc. 2024

Patents

  1. Published on 02/08/2022

    Dynamic clustering-based data compression

    USPTO#: US11245415

    Inventors: Amin Ghasemazar, Prashant Nair, Mieszko Lis

  2. Published on 08/17/2021

    Employing single error correction and triple error detection to optimize bandwidth and resilience under multiple bit failures

    USPTO#: US11095313B2

    Inventors: Prashant Nair, Robert Montoye, Jeffrey Derby, Bruce Fleischer

  3. Published on 11/10/2020

    Systems, methods and computer program products using multi-tag storage for efficient data compression in caches

    USPTO#: US10831669B2

    Inventors: Prashant Nair, Seokin Hong, Alper Buyuktosunoglu, Michael B Healy, Bulent Abali

  4. Published on 05/16/2019

    Dynamic adjustments within memory systems

    USPTO#: 2019/0146864A

    Inventors: Prashant Nair, Alper Buyuktosunoglu, Pradip Bose

  5. Published on 09/24/2019

    Bandwidth efficient techniques for enabling tagged memories

    USPTO#: 10,423,538B2

    Inventors: Prashant Nair, Bulent Abali, Pradip Bose

  6. Published on 11/06/2020

    Enabling compression based on queue occupancy

    USPTO#: US20200183620A1

    Inventors: Prashant Nair, Seokin Hong, Michael Healy, Bulent Abali, Alper Buyuktosunoglu

  7. Published on 10/29/2020

    System and method for an error-aware runtime configurable memory hierarchy for improved energy efficiency

    USPTO#: US20200342284A1

    Inventors: Alper Buyuktosunoglu, Nandini Chandramoorthy, Prashant Nair, Karthik Swaminathan

  8. Published on 04/28/2016

    Error Detection and Correction Utilizing Locally Stored Parity Information

    USPTO#: 20160117221

    Inventors: Prashant Nair and David A. Roberts

  9. Published on 05/12/2016

    Completely Utilizing the Hamming Distance for SECDED based DIMMs

    USPTO#: 20160134307

    Inventors: Prashant Nair, Chaohong Hu and Hongzhong Zheng

  10. Published on 08/14/2016

    Memory Page Access Detection

    USPTO#: US20160231933

    Inventors: Gabriel H. Loh, David A. Roberts, Mitesh R. Meswani, Mark R. Nutter, John R. Slice, Prashant Nair and Michael Ignatowski

Standards Contributions

  1. 2017–2022

    JEDEC High Bandwidth Memory 3 (HBM3) standard, JESD238

    JEDEC Solid State Technology Association

    Proposal integrating on-die and host error-correcting codes (from XED, ISCA 2016) incorporated into the HBM3 standard.

Professional Memberships

  • Senior Member IEEE, ACM

Publications

  • See the Publications tab for the full list of conference, journal, arXiv, and workshop publications.
  • Computer architecture is a conference-first field. Top international conferences are the primary channel for sharing research findings. Papers in the proceedings of these conferences, typically having acceptance rates around 20%, hold greater significance than those in journals.
  • The top conferences in computer architecture are: ISCA, MICRO, HPCA, ASPLOS.
  • I also publish in adjacent venues in Systems and Machine Learning, such as: NeurIPS, ICML, VLDB, SC, DSN, MLSys.