CV

Overview

  • Associate Professor (with tenure), University of British Columbia (UBC); Senior Principal Memory Architect (sabbatical), d-matrix Inc.
  • Awards: DSN 2025 Test of Time Award; IEEE TCCA Young Architect Award (ISCA 2024).
  • Halls of Fame: ISCA, MICRO, and HPCA (8+ papers each).
  • Publications list: see the Publications tab.

Contact

Name Prashant J. Nair
Position Associate Professor, The University of British Columbia
Website prashantnair@ece.ubc.ca
Address 4014, 2332 Main Mall, University of British Columbia, Vancouver, BC Canada V6T 1Z4

Research and Consulting Interests

  • Machine Learning Systems (LLMs, Recommenders, Diffusion Models)
    • Algorithm–memory co-design to cut data movement and latency in training/inference (e.g., compact/constant-size KV caches, embedding locality/skipping, layer reuse for diffusion/text-to-video acceleration).
  • Memory Security
    • Practical, low-overhead RowHammer defenses and timing-channel hardening for commodity DRAM and accelerators.
  • Memory Reliability
    • Robustness for AI/HPC workloads via sparsity-aware protection and mixed-precision resilience; leveraging modern on-die ECC for enhanced resiliency.
  • Sustainability in Computing
    • Reducing embodied and operational carbon in memory, storage, and machine learning training and inference pipelines.
  • Quantum Computing Systems
    • Scalable, noise-aware simulation and efficient scheduling/multiprogramming for VQA/NISQ-era systems.

Appointments

  • 2025–Present
    Associate Professor (with tenure)
    University of British Columbia (UBC)
  • 2019–2025
    Assistant Professor
    University of British Columbia (UBC)
  • 2022–Present
    Affiliate Fellow
    Quantum Algorithms Institute (QMI)
  • 2017–2019
    Post-Doctoral Researcher
    IBM T.J. Watson Research Center
  • 2012–2017
    Graduate Research Assistant
    Georgia Institute of Technology

Industry Experience

  • 2025–Present
    Senior Principal Memory Architect (on Sabbatical from UBC)
    d-matrix Inc.
  • 2016
    Research Intern
    IBM T. J. Watson Research Center
  • 2015
    Research Intern
    Intel Labs
  • 2014
    Research Intern
    Samsung Inc.
  • 2013
    Research Intern
    Advanced Micro Devices (AMD) Research
  • 2012
    Co-Op Intern
    Advanced Micro Devices (AMD) Inc.

Education

  • 2017
    Ph.D., Electrical and Computer Engineering
    Georgia Institute of Technology
  • 2013
    M.Sc., Electrical and Computer Engineering
    Georgia Institute of Technology
  • 2009
    B.Engg., Electronics Engineering
    University of Mumbai

Honors, Awards, and Impact

  • Field-wide Recognition
    • DSN 2025 Test of Time Award → Recognizes an outstanding paper published 10 years ago at DSN, in the DSN proceedings (research track, practical experience report or tool papers), that has had a sustained and important impact on the theory and/or practice of dependable systems and networks computing research.
    • TCCA Young Architect Award, the highest early career award in computer architecture, presented at ISCA 2024.
  • Hall of Fame Inductions
    • Inducted into three premier Halls of Fame in Computer Architecture during my time as a tenure-track Assistant Professor.
    • ISCA Hall of Fame → Awarded to a Researcher with 8+ papers in ISCA Conference.
    • MICRO Hall of Fame → Awarded to a Researcher with 8+ papers in MICRO Conference.
    • HPCA Hall of Fame → Awarded to a Researcher with 8+ papers in HPCA Conference.
  • Paper Awards and Distinctions
    • MICRO Top-Picks 2025 (honorable mention).
    • HPCA 2025 Distinguished Artifact Award → One of Two Distinguished Artifacts.
    • MICRO 2024 Best Paper Nominee → One of Five Best Paper Nominees in 497 Submissions.
    • HPCA 2023 Best Paper Award → One of Two Best Papers in 360 Submissions.
    • MICRO Top-Picks 2019 (honorable mention).
    • MICRO Top-Picks 2016 (honorable mention).
  • Industry Impact
    • HBM3 memory currently employs ideas from the XED paper (ISCA-2016).
  • Academic and Teaching Honors
    • ECE Graduate Research Assistant Excellence Award → Award for outstanding research accomplishments during Ph.D. at Georgia Institute of Technology.
    • Finalist at the Qualcomm Innovation Fellowship – 2014.
    • Thank a Teacher Award → For being an exemplary TA during Fall 2012.

Grants and Funding

  • 2019–2025
    NSERC – Discovery Grant (Individual)
    NSERC
    • Architectural Techniques to Sustain Moore’s Law to Enable Reliable, Secure, and Efficient Memory Systems
    • Competitive (C)
    • Principal Investigator: P. Nair (100%)
  • 2019
    NSERC – Discovery Supplement (Individual)
    NSERC
    • Architectural Techniques to Sustain Moore’s Law to Enable Reliable, Secure, and Efficient Memory Systems
    • Competitive (C)
    • Principal Investigator: P. Nair (100%)
  • 2020–2021
    DARPA (Defense Advanced Research Projects Agency)
    DARPA
    • An Optimized TensorFlow to RTML Compilation Flow
    • Competitive (C)
    • Co-Investigator(s): M. Lis, S. Wilton, S. Shekar, P. Nair (25%)
  • 2022
    Meta Inc. (Gift)
    Meta Inc.
    • Software-Hardware Strategies for Enhancing ML Application Resilience
    • Competitive (C)
    • Principal Investigator: P. Nair (50%)
    • Co-Investigator(s): K. Pattabiraman, S. Gopalakrishnan
  • 2022–2023
    National Research Council (NRC)
    National Research Council (NRC)
    • Efficient and Scalable Quantum Simulation Frameworks using Smart Data Representation and Computation Reuse
    • Competitive (C)
    • Principal Investigator: P. Nair (100%)
  • 2022–2023
    Intel Transformative Server Architecture Grant
    Intel
    • Blended Systems: Building Efficient and Secure Next-Generation Datacenter Hardware and Software
    • Competitive (C)
    • Principal Investigator: A. Fedorova (20%)
    • Co-Investigator(s): A. Alamadeen, A. Mehta, P. Nair, S. Gopalakrishnan (20%)
  • 2023
    NSERC Alliance Grant
    NSERC
    • Blended Systems: Building Efficient and Secure Next-Generation Datacenter Hardware and Software
    • Competitive (C)
    • Principal Investigator: A. Fedorova (25%)
    • Co-Investigator(s): P. Nair, A. Mehta, S. Gopalakrishnan (25%)
  • 2024
    National Research Council (NRC)
    National Research Council (NRC)
    • Paving the Path to Practical Quantum Simulations through Resource Optimizations
    • Competitive (C)
    • Principal Investigator: P. Nair (100%)

Teaching Philosophy

  • I integrate both practical and theoretical elements into my teaching. My goal is to equip students with the ability to apply concepts and solve real-world problems. My coursework emphasizes hands-on experience by incorporating industry-relevant tools. This approach enables students to use modern frameworks to learn key concepts like caching, branch prediction, and performance optimization. I also encourage students to reason about core computer architecture concepts using mathematical frameworks.
  • To foster an inclusive and engaging learning environment, I employ a variety of assessments, including quizzes, labs, and assignments, which cater to diverse learning styles. This approach ensures that students develop the technical and critical thinking skills necessary for success in academia and industry.

Teaching (UBC)

  • CPEN 511 – Advanced Computer Architecture (Graduate Course)
    • Winter 2024 T2: 21 Lectures and 5 Project Presentations, Class size: 10
    • Winter 2023 T2: 21 Lectures and 5 Project Presentations, Class size: 16
    • Winter 2019 T2: 21 Lectures and 5 Project Presentations, Class size: 16
    • Winter 2018 T2: 18 Lectures and 3 Project Presentations, Class size: 5
  • CPEN 411 – Computer Architecture
    • Winter 2024 T1: 24 Lectures and 12 Tutorial Sessions, Class size: 80
    • Winter 2023 T1: 24 Lectures and 12 Tutorial Sessions, Class size: 89
    • Winter 2022 T1: 24 Lectures and 12 Tutorial Sessions, Class size: 65
    • Winter 2021 T1: 24 Lectures and 12 Tutorial Sessions, Class size: 68
    • Winter 2020 T1: 24 Lectures and 12 Tutorial Sessions, Class size: 38
    • Winter 2019 T1: 24 Lectures and 12 Tutorial Sessions, Class size: 38
  • CPEN 311 – Digital Systems Design
    • Winter 2023 T1: 24 Lectures and 24 Lab Sessions, Class size: 113
    • Winter 2021 T2: 24 Lectures and 24 Lab Sessions, Class size: 36
  • CPEN 211 – Introduction to Microcomputers
    • Winter 2022 T1: 12 Lectures, 7 Lab Sessions, and 3 Lab Proficiency Tests, Class size: 317

Teaching Legend and Term Conventions

  • Legend
    • CPEN 211: Introduction to Microcomputers
    • CPEN 311: Digital Systems Design
    • CPEN 411: Computer Architecture
    • CPEN 511: Advanced Computer Architecture (Graduate Course)
  • Term conventions
    • Winter Term 1 (T1) starts at the beginning of September and ends in the second or third week of December, including the final exam.
    • Winter Term 2 (T2) begins in early January and concludes in the second or third week of April, also including the final exam.
    • The Winter Term T2 of the next calendar year is represented by the previous year. For example, Winter 2023 T2 occurs from January to April 2024.

Students

  • Current Students
    • Jeonghyun Woo – Ph.D. Candidate
    • Meng Wang – Ph.D. Candidate
    • Muhammad Adnan – Ph.D. Candidate, CGS-D Fellowship Holder
    • Yassaman Ebrahimzadeh Maboud – Ph.D. Candidate
    • Junsu Kim – Ph.D. Student
    • Mushahid Khan – Ph.D. Candidate, Four Year Fellowship Holder (primary advisor Prof. Olivia Di Matteo)
  • Graduated Students
    • Amin Ghasemazar (primary advisor Prof. Mieszko Lis)
    • Bolin Wang – M.A.Sc.
    • Muhammad Adnan: M.A.Sc. continued to Ph.D.
    • Yassaman Ebrahimzadeh Maboud: M.A.Sc. continued to Ph.D.
    • Ali Asgari – M.A.Sc. (primary advisor Prof. Karthik Pattabiraman)
    • Muchen He – M.A.Sc. (primary advisor Prof. Mieszko Lis)
    • Kevin Zhou – B.A.Sc. (co-supervised with Mieszko Lis)
    • Jacob Yang – B.A.Sc.
    • Irene Wang – B.A.Sc.
    • Peter Deutsch – B.A.Sc. (co-supervised with Mieszko Lis)
    • John Do – B.A.Sc. (co-supervised with Mieszko Lis)

Tools and Resources

  • HPCA 2023 and IISWC 2024: Training Big Sparse Recommendation Models on Commodity Servers — Project page
  • FaultSim: Open-Sourced Fast and Accurate Memory-Reliability Simulator (with AMD Inc.) — GitHub

Invited Talks

  • December 2024
    From Bottlenecks to Breakthroughs: Enhancing Memory Systems for Next-Gen Machine Learning
    IIT Bombay
  • November 2024
    Ender’s Game: Architectural Techniques to Develop Scalable and Secure Memory Systems
    Columbia University
  • November 2024
    Ender’s Game: Architectural Techniques to Develop Scalable and Secure Memory Systems
    Cornell Tech University
  • April 2024
    Ender’s Game: Rethinking Strategies for Crafting Secure Memory Systems
    Georgia Institute of Technology
  • November 2023
    From Bits to Beyond: Crafting Secure and Scalable Memory Architectures for Next-Generation Systems
    University of Pennsylvania
  • November 2023
    From Bits to Beyond: Crafting Secure and Scalable Memory Architectures for Next-Generation Systems
    UT Austin
  • November 2023
    From Bits to Beyond: Crafting Secure and Scalable Memory Architectures for Next-Generation Systems
    NYU
  • October 2023
    From Bits to Beyond: Crafting Secure and Scalable Memory Architectures for Next-Generation Systems
    EPFL
  • October 2023
    From Bits to Beyond: Crafting Secure and Scalable Memory Architectures for Next-Generation Systems
    d-matrix
  • May 2023
    Scaling the Memory Wall: Towards Next Generation Architecture and Systems
    AMD
  • June 2022
    Research in Academia and Industry!
    Keynote at the uArch Workshop (co-held with ISCA 2022)
  • October 2018
    Attaché: Towards Ideal Memory Compression by Mitigating Metadata Bandwidth Overheads
    MICRO-51
  • Aug. 2016
    DVoLT: Dynamic Voltage and Timing for Memory DIMMs
    IBM
  • 2016
    XED: Exposing On-Die Error Detection Information for Strong Memory Reliability
    during ISCA’16
  • Aug. 2016
    XED: Exposing On-Die Error Detection Information for Strong Memory Reliability
    IBM
  • 2016
    On Fault Simulators
    Memory Reliability Forum (Organizer & Speaker) in HPCA’16
  • 2016
    DMAT: Decoupling DRAM Mats for low-latency
    ArchiTech co-located with ASPLOS’16
  • 2015
    Reducing Read Latency of Phase Change Memory via Early Read & Turbo Read
    during HPCA’15
  • 2014
    Citadel: Efficiently Protecting Stacked Memory from Large Granularity Failures
    during MICRO’14
  • 2014
    Citadel: Efficiently Protecting Stacked Memory from Large Granularity Failures
    during Memory Forum in ISCA’14
  • 2014
    FAULTSIM: A Fast, Configurable Memory-Resilience Simulator
    during Memory Forum in ISCA’14
  • Jun. 2013
    ArchShield: Architectural Framework for Assisting DRAM Scaling by Tolerating High Error-Rates
    AMD
  • 2013
    A Case for Refresh Pausing in DRAM Memory Systems
    during HPCA’13

Academic Service

  • Program Committee Member
    • International Symposium on High-Performance Computer Architecture (HPCA) 2025
    • International Symposium on Computer Architecture (ISCA) 2025
    • International Symposium on Microarchitecture (MICRO) 2024
    • International Symposium on Computer Architecture (ISCA) 2024
    • International Symposium on High-Performance Computer Architecture (HPCA) 2024
    • International Symposium on Microarchitecture (MICRO) 2023
    • International Symposium on Computer Architecture (ISCA) 2023
    • International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) 2023
    • International Symposium on Microarchitecture (MICRO) 2022
    • International Conference for High Performance Computing, Networking, Storage, and Analysis (SC) 2022
    • IEEE Micro Special Issue on Top Picks from the 2021 Computer Architecture Conferences
    • International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) 2022
    • International Parallel and Distributed Processing Symposium (IPDPS) 2022
    • International Symposium on High-Performance Computer Architecture (HPCA) 2022
    • International Symposium on Microarchitecture (MICRO) 2021
    • International Symposium on Computer Architecture (ISCA) 2021
    • Annual Non-Volatile Memories Workshop 2021
    • IEEE Micro Special Issue on Top Picks from the 2020 Computer Architecture Conferences
    • International Symposium on Microarchitecture (MICRO) 2019
    • IEEE Transactions on Parallel and Distributed Processing Systems
    • IEEE Computer Architecture Letters
    • ACM Transactions on Architecture and Code Optimization
    • ACM Transactions on Computers
  • External Review Committee Member
    • International Symposium on Microarchitecture (MICRO) 2025
    • International Symposium on High-Performance Computer Architecture (HPCA) 2024
    • International Symposium on High-Performance Computer Architecture (HPCA) 2023
    • International Symposium on Computer Architecture (ISCA) 2022
    • International Symposium on Computer Architecture (ISCA) 2020
    • International Symposium on High-Performance Computer Architecture (HPCA) 2018
    • International Symposium on Computer Architecture (ISCA) 2016
  • Invited Reviewer
    • International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) 2016
  • Chair Roles
    • Submission Chair: International Symposium on Microarchitecture (MICRO) 2015
    • Submission Chair: IEEE Micro Special Issue on Top Picks from the 2016 Computer Architecture Conferences
    • Local-Area Co-Chair: International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) 2023
    • Finance Chair: 2024 IEEE International Symposium on Workload Characterization (IISWC)
    • Publication Chair: 32nd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems
  • Organizer
    • Tutorial on training Big Tutorial Sparse Recommendation Models on Commodity Servers (Co-held with IISWC 2023)
    • Tutorial on training Big Tutorial Sparse Recommendation Models on Commodity Servers (Co-held with HPCA 2023)
    • The Memory Reliability Forum Workshop (Co-held with HPCA 2016)

University Service

  • Internal committee member for the following students
    • Ian Hill – Ph.D. 2020–present
    • Mohammadreza Saed – Ph.D. 2020–present
    • Dingqing Yang – Ph.D. 2020–present
    • Lufei Liu – Ph.D. 2020–present
    • Mohammadhossien Olyaiy – Ph.D. 2020–present
    • Avilash Mukherjee – Ph.D. 2019–present
    • Yuan Hsi Chou – Ph.D. 2019–2025
    • Nikhil Pratap Ghanathe – Ph.D. 2019–2025
    • Deval Shah – Ph.D. 2020–2024
    • Niloofar Zarif – M.A.Sc. 2020–2023
    • Chris Ng – M.A.Sc. 2020–2022
    • Muchen He – M.A.Sc. 2020–2022
    • Zitao Chen – M.A.Sc. 2019–2020
    • Parvez Chanawala – M.A.Sc. 2020–2022
    • Niranjhana Narayanan – M.A.Sc. 2019–2021
  • External committee member for the following students
    • Abdelrahman Hussein; Simon Fraser University (SFU) - M.A.Sc. 2024

Patents

  • Published on 02/08/2022
    Dynamic clustering-based data compression
    USPTO#: US11245415
    • Inventors: Amin Ghasemazar, Prashant Nair, Mieszko Lis
  • Published on 08/17/2021
    Employing single error correction and triple error detection to optimize bandwidth and resilience under multiple bit failures
    USPTO#: US11095313B2
    • Inventors: Prashant Nair, Robert Montoye, Jeffrey Derby, Bruce Fleischer
  • Published on 11/10/2020
    Systems, methods and computer program products using multi-tag storage for efficient data compression in caches
    USPTO#: US10831669B2
    • Inventors: Prashant Nair, Seokin Hong, Alper Buyuktosunoglu, Michael B Healy, Bulent Abali
  • Published on 05/16/2019
    Dynamic adjustments within memory systems
    USPTO#: 2019/0146864A
    • Inventors: Prashant Nair, Alper Buyuktosunoglu, Pradip Bose
  • Published on 09/24/2019
    Bandwidth efficient techniques for enabling tagged memories
    USPTO#: 10,423,538B2
    • Inventors: Prashant Nair, Bulent Abali, Pradip Bose
  • Published on 11/06/2020
    Enabling compression based on queue occupancy
    USPTO#: US20200183620A1
    • Inventors: Prashant Nair, Seokin Hong, Michael Healy, Bulent Abali, Alper Buyuktosunoglu
  • Published on 10/29/2020
    System and method for an error-aware runtime configurable memory hierarchy for improved energy efficiency
    USPTO#: US20200342284A1
    • Inventors: Alper Buyuktosunoglu, Nandini Chandramoorthy, Prashant Nair, Karthik Swaminathan
  • Published on 04/28/2016
    Error Detection and Correction Utilizing Locally Stored Parity Information
    USPTO#: 20160117221
    • Inventors: Prashant Nair and David A. Roberts
  • Published on 05/12/2016
    Completely Utilizing the Hamming Distance for SECDED based DIMMs
    USPTO#: 20160134307
    • Inventors: Prashant Nair, Chaohong Hu and Hongzhong Zheng
  • Published on 08/14/2016
    Memory Page Access Detection
    USPTO#: US20160231933
    • Inventors: Gabriel H. Loh, David A. Roberts, Mitesh R. Meswani, Mark R. Nutter, John R. Slice, Prashant Nair and Michael Ignatowski

Professional Memberships

  • Senior Member IEEE, ACM

Publications

  • See the Publications tab for the full list of conference, journal, arXiv, and workshop publications.
  • Computer architecture is a conference-first field. Top international conferences are the primary channel for sharing research findings. Papers in the proceedings of these conferences, typically having acceptance rates around 20%, hold greater significance than those in journals.
  • The top conferences in computer architecture are: ISCA, MICRO, HPCA, ASPLOS.
  • I also publish in adjacent venues in Systems and Machine Learning, such as: NeurIPS, ICML, VLDB, SC, DSN, MLSys.